Semiconductor device having S/D to S/D connection and isolation region between two semiconductor elements
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United States of America Patent
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Feb 24, 2004
Grant Date -
May 1, 2003
app pub date -
Jul 11, 2002
filing date -
Nov 1, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A plurality of MOS type FET devices 14 and 16 are provided on a semiconductor substrate 12. A lower interlayer insulating film 20 is provided thereon. Each of through holes 22, which extends from each of gate electrodes 14c of the plural FET devices via source/drain regions 14b and 16a, is defined in the lower interlayer insulating film 20. A local wiring 24 is buried in the through hole 22 to connect each gate electrode 14c and the source/drain regions 14b and 16a. Further, an upper interlayer insulating film 26 is provided on the local wiring 24 and the lower interlayer insulating film 20. Upper electrode layers 28 are placed on the surface of the upper interlayer insulating film 26.
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