High speed pre-computing circuit and method for finding the error-locator polynomial roots in a Reed-Solomon decoder
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United States of America Patent
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Feb 10, 2004
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N/A
app pub date -
Nov 12, 1998
filing date -
Nov 12, 1998
priority date (Note) -
Expired
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Abstract
A system and method used in a Reed-Solomon (RS) decoder for determining roots of error locator polynomials in which a first pre-computation operation is performed to obtain a p-bit polynomial solution value in a first clock cycle and second parallel feedback logical operations are performed to obtain a p-bit polynomial solution value in each subsequent clock cycles. The system excludes constant Galois Field multipliers from the critical timing path of the system so as to facilitate high speed error-locator polynomial root determination. In the case of an unshortened RS(m,d) decoder defined over the Galois Field GF(2.sup.p) where GF(2.sup.p) is a finite field of 2.sup.p elements and m=2.sup.p -1, final root location values are obtained in m cycles. In the case of a shortened RS(n,d) decoder defined over the Galois Field GF(2.sup.p) where GF(2.sup.p) is a finite field of 2.sup.p elements and m=2.sup.p -1 and n
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