Vertical MOSFET with asymmetric gate structure
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United States of America Patent
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Feb 3, 2004
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N/A
app pub date -
Dec 20, 2002
filing date -
Dec 20, 2002
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Abstract
A semiconductor fabrication process and structure in which a semiconductor channel structure (140) having first and second major surfaces perpendicular to a semiconductor substrate (102) is formed overlying and electrically isolated from the substrate (102). First and second gate dielectrics (120, 142) are formed on the channel structure's first and second major surfaces respectively. First and second gate dielectrics (120, 142) differ in at least one characteristic. First and second gate electrodes (116, 152) are formed in contact with the first and second gate dielectrics (120, 142) respectively. The first and second gate electrodes (116, 152) differ in at least one characteristic. First and second gate dielectrics (120, 142) may have different dielectric constants while first and second gate electrodes (116, 152) may have different doping and conducting properties.
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