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Abstract

A method and algorithm to handle a memory bank queue using a low processing power 8-bit microcontroller is provided. The microcontroller is used to receive information in the form of a data packet from a communication interface shared with an external system. Each received packet is temporarily stored in a logical FIFO queue while the first packet in the queue packet is processed, modified or decoded according to a process or algorithm made by the user. The result keeps the same queue position until a second system is able to receive it through a second communication interface. In the same manner, any information packet coming from the second system is queued and processed back to retrieve a result to the first processor. This invention provides a mechanism to maintain two or more logic queues sharing the same physical RAM, one for each kind of process related to packets flowing from one interface to another. A banked memory structure is used, considering each bank as a generic memory buffer that can be occupied by any of the existing queues. Adequate information about each queue is stored to keep the queue's logic order. Appropriate low-complexity algorithms have been defined to use such information to manage the available buffers, suitable to the processing power of an 8-bit microcontroller.

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First Claim