Method for determining the optimum locations for scan latches in a partial-scan IC built in self test system
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United States of America Patent
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Nov 18, 2003
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app pub date -
May 20, 1999
filing date -
May 20, 1999
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Abstract
A method for determining optimum locations for scan latches using traditional fault-simulation and some additional `bookkeeping.` A logic simulation is run on the IC, with single stuck-at faults injected into the circuit. The entire test set is run and records are kept of which faults are detected at every latch in the system. After the simulation run, the statistics gathered are used to indicate which system latches are the best candidates for conversion to scan latches: A high count of faults indicates high observability at that point. This can be further refined by looking at total faults covered by given sets of latches. This permits maximizing fault coverage while minimizing resources. In addition, the software can keep a transition count at each latch's output, to enable the already established method of using transition counts to measure testability. A low transition count indicates a desirable place for a scan latch.
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