Electropolishing metal layers on wafers having trenches or vias with dummy structures
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United States of America Patent
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Oct 28, 2003
Grant Date -
Nov 28, 2002
app pub date -
Mar 27, 2002
filing date -
Apr 24, 2001
priority date (Note) -
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Abstract
In electropolishing a metal layer on a semiconductor wafer, a dielectric layer is formed on the semiconductor wafer. The dielectric layer is formed with a recessed area and a non-recessed area. A plurality of dummy structures are formed within the recessed areas where the dummy structures are inactive areas configured to increase the planarity of a metal layer subsequently formed on the dielectric layer. A metal layer is then formed to fill the recessed area and cover the non-recessed area and the plurality of dummy structures. The metal layer is then electropolished to expose the non-recessed area.
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