Pixel clock PLL frequency and phase optimization in sampling of video signals for high quality image display
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United States of America Patent
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Oct 14, 2003
Grant Date -
Dec 19, 2002
app pub date -
Sep 15, 1999
filing date -
Sep 15, 1999
priority date (Note) -
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Abstract
Pixel clock frequency and optimum sampling phase adjustment is an important requirement in Flat panel display monitors (FPDM) with an analog video interface. This invention proposes a new and more advanced method for frequency and optimum sampling phase determination. It is based on analyzing the content of the image to arrive at an optimum value of phase and frequency by directly optimizing image quality. The method differs from existing methods on two counts. First, no assumptions are needed about the precise value of expected frequency. Second, instead of following a two step approach of first determining frequency and then phase, this invention makes possible a single pass phase-frequency optimization.
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