Importance

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Abstract

A system and method for maintaining lock of a phase locked loop within an integrated circuit during both a normal operation mode and a test mode, and during switching from the normal operation mode to the test mode, is disclosed. The method includes closing a phase locked loop feedback path of the phase locked loop with a real clock signal from a real clock tree during the normal operation mode. The real clock tree is selectively halted, thereby transitioning from the normal operation mode to the test mode. The phase locked loop feedback path of the phase locked loop is closed with a copy of a clock signal from a copy clock tree such that the phase locked loop maintains lock. The steps of halting the real clock and closing the phase locked loop feedback path with a copy clock signal are completed during a single clock cycle such that lock is maintained during switching from the normal operation to the test mode.

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First Claim