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Abstract

A process fabricates a vertical structure high carrier mobility transistor on a substrate of crystalline silicon doped with impurities of the N type, the transistor having a collector region located at a lower portion of the substrate. The process includes: defining a window in the semiconductor substrate; providing a first implantation of germanium atoms through said window; providing a second implantation of acceptor dopants through said window to define a base region; applying an RTA treatment, or treatment in an oven, to re-construct the crystal lattice within the semiconductor substrate comprising a silicon/germanium alloy; forming a first thin dielectric layer of silicon dioxide by chemical vapor deposition; depositing a second dielectric layer onto said first dielectric layer; depositing a polysilicon layer onto said second dielectric layer; etching away, within the window region, said first and second dielectric layers, and the polysilicon layer, to expose the base region and form isolation spacers at the window edges; and forming an N-doped emitter in the base and window regions. This fabrication process is specially attentive to the formation of the silicon dioxide SiO.sub.2 /Ge.sub.x Si.sub.1-x interface present in vertical structure HBT transistors, if isolation spacers are to be formed. The fabrication process allows the frequency field of application of HBT transistors to be further extended, while eliminating deviations of the base currents from the ideal.

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First Claim