Method and apparatus for adjusting the clock delay in systems with multiple integrated circuits
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United States of America Patent
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Sep 16, 2003
Grant Date -
Feb 6, 2003
app pub date -
Mar 2, 2001
filing date -
Mar 2, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An apparatus and method for adjusting the clock delay in systems with multiple integrated circuits has a controller, a programmable clock generator and a plurality of integrated circuits, each integrated circuit including a data flip-flop, a programmable delay and a clock-fanout tree, wherein the clock delay in the integrated circuits is adjusted to match the inherent delay in the integrated circuit having the longest inherent delay.
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