BIAS FEED NETWORK ARRANGEMENT FOR BALANCED LINES
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United States of America Patent
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Sep 16, 2003
Grant Date -
Oct 9, 2003
app pub date -
Apr 3, 2002
filing date -
Apr 3, 2002
priority date (Note) -
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status (Latency Note)
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Abstract
A circuit configuration for introducing bias in balanced lines capable of high frequency operation comprises top and bottom layers formed on a semiconductor substrate. The circuit includes two balanced metallized lines positioned on the substrate. Each metallized line has a serpentine line configuration connected thereto. The space between the lines is a virtual ground. The serpentine line configurations are congruent with the elements on the substrate layers to provide a completed circuit. The elements are coupled to a central metallic area, which in turn is coupled to a bias line through an open-line stub, which extends beyond the virtual ground and which provides equal capacitive coupling to the balanced lines on the top surface. In this manner, the balanced line configuration includes capacitors and inductors which are symmetrically distributed and which provide resonance at the designed operating frequency. The bias line thus formed is RF grounded due to the virtual ground and is disconnected from the actual balanced lines.
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