Semiconductor memory device
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United States of America Patent
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Sep 9, 2003
Grant Date -
Dec 26, 2002
app pub date -
May 14, 2002
filing date -
Jun 20, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The semiconductor memory device of the present invention is provided with a switching element comprised of a single channel MOS transistor at a halfway of a path used to transmit a high voltage supplied to the memory array via the external terminal at the time of a test performance, so that the switching element is turned off when a word line is changed to another, thereby resetting of the supply voltage having been required conventionally for each test performance is omitted.
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