Embedded microprocessor multi-level security system in flash memory
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United States of America Patent
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Sep 2, 2003
Grant Date -
N/A
app pub date -
Jan 7, 2000
filing date -
Jan 7, 2000
priority date (Note) -
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Abstract
An embedded microprocessor two level security system in flash memory. The memory includes an address input and a memory space of addressable locations having a restricted area and a user area. Addressing one of a the addressable locations therein results in the output of information therefrom in response to the receipt of an associated address on the address input. A logic device is provided for determining if a received address on the address input corresponds to an attempt to access an addressable location in the restricted space for output of information therefrom as the result of execution of a program instruction from the user area by an external processor. An inhibit device is provided for inhibiting access to the addressable location if a positive determination is made by the logic device
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