Microcomputer having on-screen display
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United States of America Patent
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Aug 26, 2003
Grant Date -
N/A
app pub date -
Jun 7, 2000
filing date -
Dec 13, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A CPU outputs address data indicating a data storing unit or an OSD-RAM to access the data storing unit or the OSD-RAM, and an OSD logical circuit sometimes accesses the OSD-RAM to display data on an on-screen display. The address data is decoded in an OSD-RAM address decoder, and a decoded signal of '0' or '1' is output to an OR gate. Also, a value '0' normally set in a 1-wait register is output to the OR gate. When the address data indicates the data storing unit, a value '0' is output from the OR gate to a bus interface unit (BIU), an access mode of the CPU is set to a no-wait access mode corresponding to a shortest cycle, and the CPU accesses the data storing unit at the no-wait access mode. In contrast, when the address data indicates the OSD-RAM, a value '1' is output from the OR gate to the BIU, an access mode of the CPU is set to a 1-wait access mode corresponding to a double cycle, and the CPU accesses the OSD-RAM in the first half of the double cycle. When the accessing of the OSD logical circuit to the OSD-RAM is performed simultaneously with the accessing of the CPU to the OSD-RAM, the OSD logical circuit accesses the OSD-RAM in the second half of the double cycle. Therefore, software processing efficiency can be improved.
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