Cache memory employing dynamically controlled data array start timing and a microcomputer using the same
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United States of America Patent
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Jul 29, 2003
Issued Date -
N/A
app pub date -
Feb 28, 2002
filing date -
Jun 1, 1995
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A comparator having a hit signal that is high, before a hit check is established in each way of an address array, and that goes low, when a mishit has been established. When a clock frequency is high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check is established. When the hit check has been established, data read from a way which has the hit is output onto a data line and an operation in the way which has a mishit is stopped.
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