Image reject mixer circuit arrangements

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6597899
APP PUB NO 20020058492A1
SERIAL NO

09185838

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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An image reject mixer arrangement 1 comprises a transconductor 2, first and second mixer cores 3 and 4, first and second phase shifters 5 and 6 and a summer or combiner 7. The mixer arrangement 1 receives a single-ended RF voltage signal on a terminal 8, a differential local oscillator signal on I-LO terminals indicated at 9 and a 90.degree. phase shifted differential local oscillator signal on Q-LO terminals 10, and provides differential IF output signals on output terminals 11. From the output of the transconductor 2 to the output of the combiner 7, the image reject mixer arrangement 1 carries signals in what can be described as a 'current mode', i.e. it is the current, not the voltage, which conveys the desired signal. In this current mode, it is advantageous to provide each active circuit block with a high output impedance and a low input impedance wherever possible. This is achieved by the cascode connection of the transistors of the transconductor 2 with the transistors of the mixer cores 3 and 4; and the cascode connection of the transistors of the of the mixer cores 3 and 4 with the transistors of the combiner 7. This is advantageous in providing improved noise performance, linearity and current consumption in comparison with cascade connected mixer arrangement circuit blocks.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Graham, Stephen P Swindon, GB 8 143
Souetinov, Viatcheslav I Swindon, GB 3 222

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