Clock synchronous semiconductor memory device having a reduced access time
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United States of America Patent
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-
Jul 1, 2003
Grant Date -
Sep 6, 2001
app pub date -
Apr 30, 2001
filing date -
Jun 22, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In successively executed operations modes in a synchronous semiconductor memory device, data access time after the application of a row access command is reduced by providing a plurality of control signal lines, such as a differential pair of sense amplifier enable lines, advantageously shorting the control lines, and then driving the control lines to a predetermined voltage level after the elapse of a prescribed time period.
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