PCI bridge having latency inducing serial bus
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jun 17, 2003
Grant Date -
N/A
app pub date -
May 14, 1999
filing date -
May 14, 1999
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A computer system includes a host processor, a first PCI bus, a second PCI bus and a bus bridge. The first PCI bus is coupled with the host processor. The bus bridge interconnects the first and second PCI buses. The bus bridge includes a first portion having a first bridge memory, a second portion having a second bridge memory, and a latency inducing serial bus interconnecting the first portion and the second portion. A method is also taught.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully