High performance internal bus for promoting design reuse in north bridge chips
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United States of America Patent
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Jun 17, 2003
Issued Date -
N/A
app pub date -
May 14, 1998
filing date -
May 14, 1997
priority date (Note) -
Expired
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Abstract
In an example embodiment, an apparatus providing communication in a computer system, comprises, a plurality of modules each having a master port and a slave port A secondary bus is shared between the plurality of modules for transmitting data and address information between a master port and a slave port of two modules. A bridge circuit coupled to the plurality of modules and the secondary bus, individually grants modules of the plurality of modules, access to the secondary bus. The bridge circuit establishes point-to-point communication paths between a master port and a slave port of two modules of the plurality of modules, for communicating handshake signals between them, and controls address and data phases between modules; two address phases can be outstanding simultaneously. The bridge circuit forwards address and data phases from one module to another module of the plurality of modules; the plurality of modules only interface with the bridge circuit.
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