Method of manufacturing an EEPROM device
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United States of America Patent
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Jun 10, 2003
Issued Date -
N/A
app pub date -
Sep 23, 2002
filing date -
Dec 25, 1998
priority date (Note) -
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Abstract
A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.
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