Apparatus and method for interfacing a non-sequential 486 interface burst interface to a sequential ASB interface
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United States of America Patent
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Jun 3, 2003
Grant Date -
N/A
app pub date -
Jul 28, 1999
filing date -
Jul 28, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An apparatus is provided for interfacing a processor with a bus of a computer system wherein the processor performs burst read operations in both a sequential and a non-sequential manner and the bus is incapable of supporting burst operations that are non-sequential. The apparatus includes an interface adaptor circuit that is coupled between the processor and the bus. The interface adaptor circuit is operative as a burst order translator between the processor and the bus, and has a bridge configured to connect together the processor and the bus. The bridge is operative to translate processor burst operations into operations supported by the bus. The bridge has a processor interface coupled between the processor and the interface adaptor circuit and a bus interface coupled between the bus and the interface adaptor circuit. The bridge is operative to enable compatibility between the processor interface and the bus interface such that non-sequential burst access from the processor is supported and deliverable as sequential burst access to the bus.
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