Low defect method for die singulation and for structural support for handling thin film devices
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United States of America Patent
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-
Jun 3, 2003
Grant Date -
N/A
app pub date -
Dec 13, 2001
filing date -
Dec 13, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In certain implementations, a method for chip singulation is provided including etching a frontside dicing trench from a front side of a wafer, forming a temporary holding material, in the frontside dicing trench, etching a backside dicing trench from a back side of the wafer along the frontside dicing trench, removing the temporary holding material and releasing the chip from the wafer or an adjacent chip. Certain implementations may include etching through surface deposited layers on the front side of the wafer. Certain implementations may further include completely filling the frontside dicing trench with the temporary holding material and etching the backside dicing trench to the temporary holding material that is in the frontside dicing trench, such that removing the temporary holding material self-dices the wafer. Certain implementations may include surrounding MEMS structures with the temporary holding material so as to hold the structures during etching of the back side of the wafer. Some implementations may include providing a carrier wafer over the front side of the wafer. In certain implementations, the temporary holding material may be parylene, deposited by vapor deposition. In such implementations, the parylene may be removed by dry etching with an oxide plasma etch.
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