Semiconductor memory device capable of adjusting phase of output data and memory system using the same
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United States of America Patent
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May 27, 2003
Grant Date -
Oct 31, 2002
app pub date -
Oct 11, 2001
filing date -
Apr 25, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In a DLL circuit of a DDR SDRAM, in addition to a replica buffer for compensating delay in an output buffer, a replica buffer for compensating flight time is provided. The phase of a clock signal CLKP outputted to the outside so as to be locked with a clock signal BUFFCLK can be adjusted in accordance with a control signal b[1:0]. For a controller receiving data in a lump from a plurality of semiconductor memory devices, the arriving timings of data from the semiconductor memory devices can be aligned. Therefore, it is unnecessary to capture data in response to a data strobe signal DQS, so that burden on the controller is lessened.
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