Logic unit operable under the byzantine algorithm, computer unit having such logic unit, composite assembly comprised of logic units or computer units, and method of operating such an assembly
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United States of America Patent
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May 20, 2003
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N/A
app pub date -
May 5, 2000
filing date -
May 7, 1999
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Abstract
A logic unit operable under the Byzantine algorithm for the architectural configuration of a composite assembly which tolerates an amount of F errors in simultaneous manner as to time and a plurality of inputs for in-reading of data into registers of a set of registers, and a plurality of outputs for out-reading of data from the registers, whereby each output is connectable with an input of a further logic unit, whereby the registers are coupled with the inputs and outputs in such a manner that each register is capable of being read-in and being capable of being read-out independently of the position of the logic unit within the assembly, by means of a position invariant, relative identification, as well as a computer unit with such a logic unit, as well as the fault-tolerant assembly of such logic/computer units, and a method of operating a fault tolerant assembly.
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