Integrated circuit with silicided ESD protection transistors
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 20, 2003
Grant Date -
Oct 3, 2002
app pub date -
Sep 7, 2001
filing date -
Mar 30, 2001
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An electrostatic discharge (ESD) protection circuit for protecting an internal device from an ESD is disclosed. The ESD protection circuit includes an NMOS transistor connected to a ground voltage terminal having silicide layers on a gate electrode and on source/drain regions thereof; and a PMOS transistor having a gate electrode connected to a ground voltage terminal and connecting the NMOS transistor to a pad.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully