Memory device with variable bank partition architecture
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United States of America Patent
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May 6, 2003
Grant Date -
N/A
app pub date -
Mar 31, 2000
filing date -
Apr 1, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In a memory device with variable bank partition architecture, a plurality of bank level signals each of which specifies a number of bank divisions are input from the respective bank level terminals. Further, a plurality of address signals, each of which specifies one of the banks, are input from the address terminals. Data input from data input/output terminals are stored in batch in all access units in a memory address area corresponding to a bank specified by a bank address signal among those obtained by dividing a memory address space or an upper bank based on bank level signals.
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