Double data rate synchronous memory with block-write
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United States of America Patent
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May 6, 2003
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N/A
app pub date -
May 18, 1999
filing date -
May 19, 1998
priority date (Note) -
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Abstract
A method and apparatus for performing a block-write to a memory device comprising at least one register, a data input port, at least one memory bank, and a hardware device to block-write data from the register to the memory device, including receiving a first portion of block-write data from a data bus during a first half of a clock cycle; then, producing a second portion of the block-write data, and block-writing the first and second portions of the block-write data from a write logic unit to the memory bank at a double data rate as determined by the clock cycle.
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