MOS integrated circuit with reduced ON resistance

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United States of America Patent

PATENT NO 6552392
SERIAL NO

09899332

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Abstract

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An integrated circuit having a high voltage lateral MOS with reduced ON resistance. In one embodiment, the integrated circuit includes a high voltage lateral MOS with an island formed in a substrate, a source, a gate and a first and second drain extension. The island is doped with a low density first conductivity type. The source and drain contact are both doped with a high density second conductivity type. The first drain extension is of the second conductivity type and extends laterally from under the gate past the drain contact. The second drain extension is of the second conductivity type and extends laterally from under the gate toward the source. A portion of the second drain extension overlaps the first drain extension under the gate to form a region of increased doping of the second conductivity type.

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Patent Owner(s)

Patent OwnerAddress
INTERSIL AMERICAS LLC1001 MURPHY RANCH ROAD MILPITAS CA 95035

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Beasom, James D Melbourne Village, FL 105 1170

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