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Abstract

This invention discloses a method of making a nonvolatile memory device, wherein the capacitance between the floating gate and the substrate is reduced to result in a high capacitive coupling ratio. First, a substrate with shallow trench isolation (STI) structures protruding above the substrate and a conductive layer confined between the STI structures is provided. The conductive layer is recessed below the STI structures to leave a recess. A spacer is formed on the sidewalls of the recess to serve as an oxidation mask for the underlying conductive layer. A thermal oxide layer is grown on the conductive layer where it is not covered by the spacer, and the spacer is then removed. An opening is etched through the conductive layer using the thumal oxide layer as an etch mask to define a floating gate. After removing the oxide layer, a thin inter-gate dielectric layer and a control gate layer are sequentially formed.

First Claim