Level sensitive latch
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United States of America Patent
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Apr 1, 2003
Grant Date -
Oct 24, 2002
app pub date -
Dec 10, 2001
filing date -
Dec 21, 2000
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A binary digital logic level sensitive latch comprising a first inverter that provides an output (O.sub.1). At least one input signal (I.sub.1) and an activation signal (Clk) are provided to the first inventer both being capacitively coupled to an input of the first inverter and a switching threshold of the first inverter. The capacitance of the couplings being predetermined such that the output of the first inverter (O.sub.1) is a NOR function of the inputs signals and the activation signal O.sub.1 =I.sub.1 +Clk. A second inverter has as inputs capacitively coupled the output of the first inverter (O.sub.1), the activation signal (Clk) and an inverted pervious output signal (P) to provide output (O.sub.2). A switching threshold of the second inverter and the capacitance of the couplings being predetermined such that the output of the second inverter (O.sub.2) takes the function of: O.sub.2 =(Clk.times.P)+O.sub.1.
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