Planar structure for non-volatile memory devices
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United States of America Patent
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Apr 1, 2003
Grant Date -
May 30, 2002
app pub date -
Jun 27, 2001
filing date -
Nov 28, 2000
priority date (Note) -
Expired
status (Latency Note)
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Abstract
One aspect of the present invention relates to a non-volatile semiconductor memory device, containing a substrate, the substrate having a core region and a periphery region; a charge trapping dielectric over the core region of the substrate; a gate dielectric in the periphery region of the substrate; buried bitlines under the charge trapping dielectric in the core region; and wordlines over the charge trapping dielectric in the core region, wherein the core region is substantially planar.
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