Wordline decoder for flash memory
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United States of America Patent
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Mar 18, 2003
Grant Date -
Dec 20, 2001
app pub date -
Feb 16, 2001
filing date -
Feb 16, 2000
priority date (Note) -
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Abstract
A wordline decoder for high density flash memory is described with negative voltage capability for memory operations such as erase. A main decoder is shared with a plurality of wordline driver circuits to reduce wiring congestion and overall layout size. In a second embodiment, a wordline decoder for fast read access is provided in which a high speed positive voltage decoder is separate from the negative voltage decoder with the addition of a triple well NMOS transistor into the inverter driver circuits. The use of triple well NMOS transistors reduces circuit and layout complexity.
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