Method for reducing base to collector capacitance and related structure
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United States of America Patent
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Mar 18, 2003
Grant Date -
N/A
app pub date -
May 7, 2001
filing date -
May 7, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
According to a disclosed embodiment, a transistor region comprising a collector region is opened adjacent to an oxide region. The oxide region may be, for example, a field oxide region. Additionally, an extrinsic collector region is formed under the oxide region. A blanket layer of dielectric is deposited over the transistor region and the oxide region. The blanket layer of dielectric can comprise, for example, silicon dioxide. The blanket layer of dielectric is etched away from the transistor region, leaving behind a dielectric segment on the oxide region. Following, a base region comprising, for example, single-crystal silicon-germanium, is grown over the collector region. Concurrently, a conductive region that is electrically connected to the base region is formed over the oxide region. The dielectric segment on the oxide region increases the separation between the conductive region and the extrinsic collector region, thus lowering the base to collector capacitance.
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Patent Citation Ranking
- 24 Citation Count
- H01L Class
- 65.46 % this patent is cited more than
- 22 Age