Method for fabricating local metal interconnections with low contact resistance and gate electrodes with improved electrical conductivity
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United States of America Patent
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Mar 18, 2003
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N/A
app pub date -
Jan 25, 1999
filing date -
Jan 25, 1999
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Abstract
A method for making low sheet resistance local metal interconnections and improved transistor performance is described. The method involves patterning a polysilicon layer and a silicon nitride (Si.sub.3 N.sub.4) cap layer over device areas to form FET gate electrodes, and the patterned polysilicon extends over the field oxide regions to form portions of the local interconnections. After forming source/drain areas and sidewall spacers on the FET gate electrodes, a silicon oxide (SiO.sub.2) insulating layer is deposited and polished back to the Si.sub.3 N.sub.4 cap. The Si.sub.3 N.sub.4 is then selectively removed over the patterned polysilicon layer, leaving recesses in the SiO.sub.2 layer. After etching contact openings in the SiO.sub.2 layer to the substrate, a high electrically conducting metal layer, having a barrier layer, is deposited and patterned to complete the local interconnections. Portions of the metal are retained in the recesses over the pattered polysilicon layer to improve transistor performance, while portions of the metal in the contact openings provide low-contact resistance to the substrate.
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