Volume rendering pipeline
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United States of America Patent
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Mar 11, 2003
Issued Date -
N/A
app pub date -
May 20, 1999
filing date -
Nov 12, 1998
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Abstract
A plurality of identical rendering pipelines are connected in parallel to read an array of voxels and to write an array of pixels. Each pipeline processes one voxel in one processing cycle of the pipelines. Each pipeline includes a plurality of serially connected different stages. The stages can include interpolation, classification, gradient estimation, illumination, and compositing stages. Interfaces connect identical stages in adjacent pipelines as one-way rings to communicate information associated with spatially adjacent voxels, and delay buffers connected parallel to particular stages communicate information associated with temporally adjacent voxels.
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