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Abstract

An equalizer based symbol timing loop system incorporates existing receiver architecture to modify an input sample stream to match a transmitter's symbol rate. The system includes a phase detector that identifies a center tap in a linear equalizer in the receiver and then captures the value of the center tap at the beginning and end of a measurement period. The phase detector then multiples the captured value of the center tap at the end of the measurement period by the conjugate of the captured center tap value at the beginning of the measurement period. The phase detector then takes the arc tangent of the multiplication result. A loop filter coupled to the phase detector multiples the arc tangent result by a scalar and adds the result to a frequency difference estimate. A coefficient generator then determines the interpolation phase for an input sample stream based on the frequency difference estimate and generates interpolator coefficients based on the interpolation phase. A timing interpolator filter coupled to the coefficient generator receives the input sample stream and interpolator coefficients and modifies the input sample stream to match the transmitter's symbol rate.

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First Claim