Erase method for flash memory
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United States of America Patent
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Feb 25, 2003
Grant Date -
Apr 25, 2002
app pub date -
Oct 12, 2001
filing date -
May 30, 1996
priority date (Note) -
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Abstract
A method of erasing electrically a programmable memory cell which cell includes a transistor formed in a region of semiconductor material. The transistor has a source region, a drain region, a floating gate, and a control gate. The method comprises lowering the control gate to a potential of about -9 volts, disconnecting the source and drain regions from any potential source, and placing the region of semiconductor material at a potential of about 9 volts.
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