Method for manufacturing wafer level chip size package
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United States of America Patent
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Feb 18, 2003
Grant Date -
Jul 18, 2002
app pub date -
Jan 17, 2001
filing date -
Jan 17, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method for manufacturing a wafer level chip size package and the method comprises the steps of: securing wafer to a partly etched lead frame, drilling blind hole and filling conductive material after packaging the lead frame to electrically connect the lead frame and the wafer, thus providing inner electrical connection of the wafer after packaging.
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