Semiconductor device including internal potential generating circuit allowing tuning in short period of time and reduction of chip area
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United States of America Patent
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Feb 4, 2003
Issued Date -
N/A
app pub date -
Nov 13, 2001
filing date -
Jul 26, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
When a tuning mode signal VTUNE is activated, control clock signal TCLK is output, and counter counts up tuning signals TSIG1 to TSIG4. Tuning circuits render conductive the terminals of respective transistors, and reference potential Vref lowers in accordance with the reduction in the resistance value. When reference potential Vref attains equal to the external reference potential Ext.Vref, differential amplifier circuit stops output of the control clock signal TCLK. In accordance with the plurality of the determined tuning signals TSIG1 to TSIG4, fuse elements inside the tuning circuits are programmed.
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