Method and apparatus for rendering an IC design layout employing graphics files at low zoom-in factors
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United States of America Patent
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Jan 21, 2003
Grant Date -
N/A
app pub date -
Oct 3, 2000
filing date -
Oct 3, 2000
priority date (Note) -
Expired
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Abstract
A method and apparatus for rendering an integrated circuit design layout is described. Graphics files are generated for selected zoom-in factors from cell-based information of the integrated circuit design, and stored in memory. When a computer operator selects a zoom-in factor greater by a predetermined amount than the largest of such selected zoom-in factors, a selector enables a rendering engine to render the integrated circuit design layout from the cell-based information. On the other hand, when the computer operator selects a zoom-in factor less than the largest of such selected zoom-in factors plus the predetermined amount, the selector enables a graphics processor to render the integrated circuit design layout from appropriate ones of the graphics files.
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