Method for generating information for a window view of an integrated circuit from layout-formatted data

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United States of America Patent

PATENT NO 6507940
APP PUB NO 20020166102A1
SERIAL NO

09847621

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Abstract

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A method generates information for a window view of an integrated circuit from layout-formatted data such as GDSII formatted data. The method includes generating outer boundary boxes for structures of the integrated circuit from the layout-formatted data, generating a build file by including information of structures having outer boundary boxes completely or partially in a window, and generating information of the window view from the information thus included in the build file. In generating the build file, information of structures having outer boundary boxes completely outside the window are excluded from the build file. Also excluded is information of structures having areas less than a threshold value.

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Patent Owner(s)

Patent OwnerAddress
ORIDUS INC39560 STEVENSON PLACE STE 221 FREMONT CA 94539

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Tsung-Yen(Eric) Fremont, CA 9 298
Du, Yu Fremont, CA 120 683
Gu, Ke-Qin San Jose, CA 7 82
Lee, Kuo-Chun Fremont, CA 402 4137

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