Complementary accumulation-mode JFET integrated circuit topology using wide (>2eV) bandgap semiconductors
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United States of America Patent
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Jan 7, 2003
Grant Date -
Sep 5, 2002
app pub date -
Mar 2, 2001
filing date -
Mar 2, 2001
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Abstract
A method and device produced for design, construction, and use of integrated circuits in wide bandgap semiconductors, including methods for fabrication of n-channel and p-channel junction field effect transistors on a single wafer or die, such that the produced devices may have pinchoff voltages of either positive or negative polarities. A first layer of either p-type or n-type is formed as a base. An alternating, channel layer of either n-type or p-type is then formed, followed by another layer of the same type as the first layer. Etching is used to provide contacts for the gates, source, and drain of the device. In one variation, pinchoff voltage is controlled via dopant level and thickness the channel region. In another variation, pinchoff voltage is controlled by variation of dopant level across the channel layer; and in another variation, pinchoff voltage is controlled by both thickness and variation of dopant level.
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