Memory architecture and addressing for optimized density in integrated circuit package or on circuit board
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United States of America Patent
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Dec 17, 2002
Issued Date -
N/A
app pub date -
Feb 2, 2001
filing date -
Jun 30, 1998
priority date (Note) -
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Abstract
An electrically erasable and programmable read only memory (EEPROM) or other memory integrated circuit (IC) includes memory cells arranged in N blocks. The number of blocks, N, is selected to maximize utilization of the space available in a standard IC package. The number of blocks need not be an even power of two. More than log.sub.2 (N) address bits are used to select between the blocks. A plurality of such memory ICs forms an array addressed by a memory controller, providing a number of directly addressable memory locations that need not be an even power of two. Addressing is provided for decoding chip select lines, block select lines, and other address lines. Staggered block decode lines associated with the memory blocks allow juxtaposition of the blocks to form a row in which connections are easily verified.
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