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Abstract

A phase locked loop is provided that includes a phase detector, an integrator, a voltage controlled oscillator and a feedback circuit. The phase detector is coupled to a reference clock signal and a feedback signal, and generates positive and negative phase detection signals that correspond to the phase difference between the reference clock signal and the feedback signal. The integrator is coupled to the positive and negative phase detection signals, and converts the positive and negative phase detection signals into an output voltage that is proportional to the phase difference between the reference clock signal and the feedback signal. The voltage controlled oscillator is coupled to the output voltage of the integrator, and generates a local oscillator signal with an oscillation frequency that is proportional to the output voltage of the integrator. The feedback circuit is coupled to the local oscillator signal, and shifts the phase of the local oscillator signal to generate the feedback signal. The phase locked loop locks with a continues phase error between the feedback signal and the reference signal that is substantially equivalent to an integer multiple of the period of the local oscillator signal.

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First Claim