Circuit and method for partial product bit shifting
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United States of America Patent
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Oct 1, 2002
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N/A
app pub date -
Sep 22, 1998
filing date -
Sep 22, 1998
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Abstract
A circuit for shifting the number of partial product bits per column in an adder tree is provided. A partial product bit is generated having a weight 2.sup.2k that has a 1 value only if one input bit of weight 2.sup.(k-1) has a 0 value while another input bit of weight 2.sup.k has a 1 value. Another more significant partial product bit of weight 2.sup.(2k+1) receives the same input bits and has a 1 value only if both of the input bits have a 1 value. In this manner, the number of partial product bits in the column of weight 2.sup.2k is decreased by 1 while the number of bits is the column of weight 2.sup.(2k+1) is increased by 1. Therefore, if the column of weight 2.sup.2k had the greatest number of partial product bits of all columns, and if the column of weight 2.sup.(2k+1) had at least two fewer bits than the column of weight 2.sup.2k, the total maximum number of bits for all the columns is reduced by 1.
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