Method and apparatus for bitstream decoding
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Oct 1, 2002
Grant Date -
N/A
app pub date -
Jan 28, 2000
filing date -
Jan 28, 2000
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A decoder for decoding a compressed incoming interruptible bitstream is disclosed. The decoder includes an input register that is capable of receiving a latch command, and that is further capable of latching stored data in a particular state upon receiving the latch command. The decoder also includes decoding logic, such as variable length decoding logic, or run-length decoding logic, in communication with the input register. Further included in the decoder is an output register in communication with decoding logic, that is also capable of receiving the latch command, and that is further capable of latching stored data in a particular state upon receiving the latch command. Finally, the decoder includes a register controller in communication with both the input register and the output register. The register controller is capable of receiving a halt command from the system and, upon receiving the halt command, the register controller sends the latch command to both the input register and the output register.
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