Semiconductor memory device allowing simultaneous inputting of N data signals
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United States of America Patent
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Sep 17, 2002
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N/A
app pub date -
Oct 19, 2001
filing date -
Apr 24, 2001
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Abstract
The SDRAM is provided with a decoder for generating four inversion instruction signals corresponding to four data signals according to a column address signal not used for a column select and a word configuration activating signal, and a data inverting circuit for outputting each data signal inverted or uninverted according to four inversion instruction signals. Thus, four data signals of the 'H' level can be input so as to write in a desired test pattern with ease.
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