Timing adjustment method and apparatus for semiconductor IC tester
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Sep 10, 2002
Grant Date -
N/A
app pub date -
Jun 20, 2000
filing date -
Sep 30, 1999
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A comparator (30) is connected through switches (13, 14 and 15) with two or more drive-only pins, and the comparator 30 is shared by two or more drive-only pins by changing the switches (13, 14 and 15). The switches are changed one by one and the signal judgment system deskew is carried out on the drive-only pin, which is connected with the comparator. Then, the switches are changed one by one similarly and the signal supply system deskew is carried out using the result of the signal judgment system deskew. Even if the semiconductor IC tester has the drive-only tester pins, the timing adjustment can be performed by carrying out the signal judgment system deskew and the signal supply system deskew.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully