PLL circuit
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United States of America Patent
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-
Aug 27, 2002
Grant Date -
N/A
app pub date -
Dec 28, 2000
filing date -
Jun 30, 1998
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An A/D converter (30) samples an analog signal synchronously with a sampling clock from a VCO (70). These sampled values are stored in a shift register (410). A code judging section (420) detects the positive/negative sign pattern (time-series code pattern) of the sampled values held in storage elements (S0 to S5) of the shift register (410) and stores the sampled values in predetermined register (431 to 434) according to the detected sign pattern. According to this, a calculating section (430) determines the phase difference between the analog signal and the sampling clock. The phase difference is fed to a VCO (70) through a D/A converter (50) and a loop filter (60).
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