Importance

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Abstract

A circuit arrangement for the fault tolerant execution of digital computer programs includes a plurality of arithmetic logic units embodied as processor pool elements connected together so that they can each execute the program in parallel. The processor elements are connected to each other through respective data, clock and reset cross-strapping interconnect lines, and are each connected to one or more serial field buses. Each processor element includes at least one microprocessor controller for controlling the functions of the processor element in such a manner that any selected number of the processor elements can be automatically actuated at any time to simultaneously execute the program in parallel and thereby achieve a prescribed degree of redundancy in the circuit arrangement. The data cross-strapping line transmits data among the several processor elements, the clock signal cross-strapping line achieves a compelled synchronization of all of the processor elements, and the reset cross-strapping line carries out the deactivation of any processor element that is recognized as carrying out a faulty execution of the program or that is not necessary for achieving the required degree of redundancy. A deactivated processor element may later be reactivated to again participate in the parallel execution of the program.

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First Claim